`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/23 20:11:50
// Design Name: HW3
// Module Name: shift_register_8bit
// Project Name: hw3
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: Homework 3 for Fudan PLD & HDL courses
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module shift_register_8bit(
    input clk,              //时钟
    input dir,              //寄存器移位方向控制信号dir。规定dir=1时左移，dir=0时右移
    input rst_n,            //复位信号rst_n
    output [7:0] D          //寄存器输出信号D[7:0]，共8位
    );
    
    reg [7:0] D;
    reg one_bit_buffer;     //使用一个1bit的buffer储存移位数据

    always @(posedge clk or negedge rst_n) begin
        if(rst_n) begin
            D <= 8'b00000001;
            one_bit_buffer <= 1'b0;
        end
        else if(dir) begin//左移
            one_bit_buffer <= D[7];
            D[7] <= D[6];
            D[6] <= D[5];
            D[5] <= D[4];
            D[4] <= D[3];
            D[3] <= D[2];
            D[2] <= D[1];
            D[1] <= D[0];
            D[0] <= one_bit_buffer;
        end
        else begin//右移
            one_bit_buffer <= D[0];
            D[0] <= D[1];
            D[1] <= D[2];
            D[2] <= D[3];
            D[3] <= D[4];
            D[4] <= D[5];
            D[5] <= D[6];
            D[6] <= D[7];
            D[7] <= one_bit_buffer;
        end
    end
endmodule
